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    /2 Technological developments of 3C–SiC thermal devices/2.1 Resistors from 3C–SiC films epitaxially grown on silicon

    #2.1 Resistors from 3C–SiC films epitaxially grown on silicon

    #2.1.1 Heteroepitaxy of 3C–SiC on silicon wafers

    #2.1.1.1 CVD Reactor

    #2.1.1.2 -> Data de Marc ?

    #2.1.2 Development of a fabrication process for suspended 3C–SiC resistors

    Because the AIMAN-FILMS group had no prior research experience in using SiC, this work starts with the development of a recipe to start etching SiC. The Oxford PlasmaLab 80 was chosen as the platform for this process, because of its availability and ease of use for a quick iterative roadmap. In order to converge towards an etching recipe that yields a good compromise between etch rate, wall slope and bottom surface quality, an iterative experimental process was defined. A masking pattern defining lines of various widths is created by metal evaporation and lift-off. The wafer is then cleaved to produce many test samples. A given RIE recipe is tested on one sample, which is cleaved again across the lines to be able to inspect a cross-section using a SEM. This enables to measure the cavity depth, the selectivity of the etching rate of SiC relative to the metal mask, and the cavity slope. Iteratively, a new sample undergoes a variation of the recipe, and progress is tested the same way. The global process flowchart is shown figure 2.1, while the results for each iteration is detailed on the following sections.

    Si Al 3C–SiC 200 nm Evaporation of Al& lift-off Various RIE recipesfor SiC etching Test patterns etched 3C–SiC heteroetpitaxy on Si
    Figure 2.1.
    Line pattern masking and fabrication for RIE tests.

    #Metal masking

    Because O2 plasma forbids photoresist masking, a metal hard mark should be used instead. The literature suggests nickel and aluminum as the best metals for this case (Pan & Steckl 1990)110. Preliminary tests were executed to assess the selectivity and potential metal micro-masking. While aluminum produces alumina particles under 02 plasma that tend to settle on the bottom of etch cavity (figure 2.2), in this particular case, nickel showed to produce much more micro-masking that produced an unsuitable amount of grass in the etching cavity. The alumina beads produces by aluminum micro-masking were much more manageable

    The aluminum mask was patterned using an evaporation/lift-off process. First, a LOR 10A / AZ 1512 photoresist bilayer is spin-coated on the SiC/Si wafer, with respectively 4-minute 180 °C and 1-minute 110 °C bakes for each layer. The resist is exposed on a Kloé Dilase 650 UV laser writer, then developed in AZ 726 MIF solution. The result is a T-top profile suited for evaporation, as it lets the metal sit cleanly in the opening by preventing wall formation. After development, a bilayer of 20 nm chromium / 200 nm aluminum is evaporated on a Plassys MEB 550SL tool. The sacrificial chromium layer serves to chemically remove the mask in hydrochloric acid,on the SiC layer is etched. The evaporated mask is finally patterned by lift-off in a heated SVC-14 bath.

    Figure 2.2.
    SEM details of the etching cavity, highlighting the micromasking effect with both aluminum and nickel masks.

    (a) Etch cavity with aluminum masking.
    (b) Etch cavity with nickel masking. The “grass” is very prominent.

    #Reactive Ion Etching

    A review of state-of-the-art techniques for anisotropic etching SiC thin films (Pan & Steckl 1990)110, (Flemish et al. 1996)111, (Wang et al. 1998)112 indicates that RIE with various mixtures of SF6, CHF3, O2 and inert gases successfully etches SiC thin films. Table 2.1 below lists all process runs with their parameters and given etch rates. The first recipe tested was a mixture of CHF3/O2, show to work well by Pan & Steckl (1990)110.

    Etch rate measurement and quality control by The top bright layer is the metal mask, the light gray layer just below is the SiC film. The silicon substrate is the dark gray layer on the bottom of the image.
    Figure 2.3.
    Etch rate measurement and quality control by SEM. The top bright layer is the metal mask, the light gray layer just below is the SiC film. The silicon substrate is the dark gray layer on the bottom of the image.
    Table 2.1.
    RIE parameters fine-tuning for etching heteroepitaxially grown 3C–SiC thin films. The etch rate is mainly dependent to the flow rate of O2 in the chamber. The introduction of argon and power increases have little effect on the etching speed, but considerably improves the wall slope aspect ratio.
    RF Power (W) Pressure (mTorr) O2 (sccm) CHF3 (sccm) Ar (sccm) Obtained etch rate (nm/min)
    300 20 18 2 0 ~0.0
    200 50 45 5 0 17.0
    300 150 45 5 0 12.0
    200 150 45 5 5 15.0
    250 150 45 5 5 15.0
    250 100 45 5 5 12.6
    150 50 45 5 5 5.4

    #3C–SiC suspended wires

    Once a satisfactory RIE recipe settled, as similar process flowchart detailed in figure 2.4, was established to produce simple SiC resistors. An additional XeF2 isotropic vapor etching step was added after chip dicing to make the wires suspended. Wires of 50, 100, 150, 200, 250 and 500 µm length and 6 µm width were produced this way. A SEM detail of one wire is shown figure 2.5. Here, the 800 nm-thick epitaxial layer of 3C–SiC has shown to structurally hold itself, without depending on an additional mechanical support to achieve wire suspension. Another fabrication test has shown that 1 mm-long wire also holds structurally. The SiC/Si lattice mismatch works in favor of the wire’s structural integrity, because of the SiC film being strained in tension rather than in compression. As a consequence, the wire is “taut” by its supports.

    3C–SiC heteroetpitaxy on Si Evaporation of Al& lift-off RIE of SiC Al mask removal XeF2 isotropic Si etching –wire release Obtaineddevice Si Al 3C–SiC 200 nm suspendedSiC wire contact pads
    Figure 2.4.
    Fabrication flowchart for a simple SiC suspended wire.
    detail of one suspended wire.
    Figure 2.5.
    SEM detail of one suspended wire.

    #2.1.2.1 Remarks on the etching process of SiC

    As figure 2.5 shows, the surface quality of the cavity created by XeF2 vapor is quite porous, most likely due to mask redeposition in the cavity floor during the RIE step (figure 2.6 (a)). An attempt to smooth the cavity bottom was made by baking the chips on a tubular oven at 1 300 °C for 15 minutes. As expected, the silicon pores were smoothed out, but it seems like silicon nano-wires have grown, seeded by the deposited mask particles (figure 2.6 (b)). This is not a limiting issue for this specific process on its own. Although, the etching method for SiC is later changed, mainly for a reason detailed later (section reference ???).

    (a) detail of the wire just after the step with aluminum masking.
    (b) The same wire suspended and baked at 1 300 °C for 15 minutes. The white particles have become seed for nanowires growth.

    Figure 2.6.
    Side effects of using an aluminum mask for etching SiC.

    #2.1.3 Current leakage through the silicon substrate

    #2.1.3.1 Characterization setup

    After fabrication, the chips are placed in a Nextron micro-probe station (figure 2.7), which has needle probe tips to precisely get the electric contacts. Current-voltage measurement points are performed by a SMU, here a National Instruments PXIe-4142 or a Keithley Model 2450 used interchangeably, plugged to the station’s coaxial ports. The probing station is equipped with a Peltier element buried underneath the test platform, which is regulated for temperature ranging from ambient to 700 °C.

    Nextron micro-probe station with heating control, to measure the resistance-temperature characteristics. The measurements are performed of a PXIe-4142 4-channel
    Figure 2.7.
    Nextron micro-probe station with heating control, to measure the resistance-temperature characteristics. The measurements are performed of a PXIe-4142 4-channel SMU.

    Because hot wires or films sensors rely on the thermoelectric effect, the key indicator of their sensitivity is the TCR. In order to accurately measure it, the electric resistance is probed with the SMU for different substrate temperatures. For metals, where this characteristic is linear, a regression enables to calculate the slope coefficient, which is divided by the base resistance at room temperature to obtain the TCR. For semiconductors like SiC, the resistance-temperature characteristic is expected to be non-monotonous, the TCR depends of the temperature and the base resistance R_0 at ambient, with the relation

    \text{TCR}(T) = \frac{1}{R_0} \frac{\text{d}R}{\text{d}T}.

    2026-09-12T13:33:30.693904 image/svg+xml Matplotlib v3.10.1, https://matplotlib.org/ 5 10 15 20 25 Wire resistance (kΩ) linear fit: slope = 517.0 kΩ/cm measurement points 100 200 300 400 500 Wire length (µm) 0.05 0.06 0.07 0.08 M e a s u r e d   r e s i s t i v i t y   (   Ω   c m ) 1 0 − 2 0
    Figure 2.8.
    Measured resistance and calculated resistivity for SiC suspended wires of various lengths and 6\dot0.8 µm section area.

    The resistance is measured for each wire length, first at ambient temperature. The results are show figure 2.8. The resistance-length characteristic is linear, however there seem to remain an contact resistance of approximately R_\text{c} = 1.9 kΩ. This is likely due to the poor quality of the ohmic contact between the SiC surface and the probe needle. The resistivity of this epitaxial layer of SiC is also much greater than that of metals: a similar geometry made of gold or platinum would be on the order of 100 Ω, whereas here it is on the order of 10 kΩ.

    #2.1.3.2 Resistance drops after 150 °C

    The resistances for wire length are measured relative to the temperature, the results for 100, 200, 250 and 500 µm are shown in figure 2.9 (b). While the non-linear aspect of the resistance-temperature characteristic is expected, the measured resistances significantly drop after 150 °C, to be all near-zero at 500 °C. This phenomenon is attributed to the silicon substrate acting as a parallel resistance, which greatly decreases as the temperature increase (figure 2.9 (a)). Here, we confirm the well-known issue discussed in the literature review, which prevents the simple measurement of a resistance made of epitaxial layers of SiC on silicon.

    Figure 2.9.
    Current leakage phenomenon observed with SiC/Si wires.

    currentin Total resistance decreases when substrate is heated due to leaks through SiC/Si interface. probe needles current through SiC wire leaks through Si substrate SiC currentout Si

    (a) Current leakage issue.
    2026-09-12T13:53:35.281822 image/svg+xml Matplotlib v3.10.1, https://matplotlib.org/ 100 200 300 400 500 Temperature (°C) 0 5 10 15 20 25 Resistance (kΩ) Si layer leaks current wire length (µm) 100 200 250 500

    (b) Resistance relative to temperature for the array of SiC resistors. The resistance completely plummets after 150 °C, which is due to current leakages in the silicon.

    #2.1.3.3 Resistance is heavily light-dependent

    As a side effect, the electric resistance also greatly varies relative to light exposition. A simple desk light used on the characterization setup, when switched on and off, makes the resistance jump to 300 % of its value in the dark.

    –> inclure la figure