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    /2 Technological developments of 3C–SiC thermal devices/2.4 Fabrication of SiC calorimeters

    #2.4 Fabrication of SiC calorimeters

    #2.4.1 Design

    Although the lithographic steps were iteratively tested on a Kloé Dilase D650 laser writer, the final design (shown in figure 2.2) was etched into two 100-mm chromium photomasks, with the help of Jean-Claude Gerbedoen at Institut ONCOLille. This enabled quick, cheap and reproductible lithographic steps.

    500 µm
    Figure 2.2.
    Detail of the GDSII design for a single SiC calorimeter chip. In purple, the design for contact pads (positive mask). In pink and brown, the pattern for opening the SiC/Si layers and defining the wires (negative mask).

    #2.4.2 SoI insulation

    #2.4.3 Highly resistive 3C–SiC buried layer insulation

    #2.4.4 Transfer to borosilicate glass

    The same insulation as presented in section ¿sec:glass_transfer? was reused, with technological adaptations to accomodate for the closely placed wires.

    The detailed steps of the fabrication process are listed below, and summarized in the fabrication flowchart in figure 2.3.

    LOR 10A / AZ1512optical lithography AZ 15nXToptical lithography AZ 726 MIFdevelopment AZ 326 MIFdevelopment SiC + Si deep etching w/ Bosch process Wafer cleaning + dicing XeF2 wire release on diced chips Perspective view Silicon ⟨100⟩ Si wafer SiCoI wafer preparation Au ohmic contacts patterning Calorimetric structure definition Wire release & final device 1 µm 3C–SiC heteroepitaxy at CRHEA, polished to 800 nm by NovaSiC Backside grinding & polishing 5 nm Ti /250 nm Au evap. Lift-off in SVC-14stripper Anodic bonding to a borosilicate wafer 3C–SiC Borosilicate glass Photoresist Ti/Au
    Figure 2.3.
    Detailed fabrication flowchart for the 3C–SiC calorimeter.
    Custom bonding setup built by Aurélien Mazzamurro, which served for anodically bond the SiC/Si stack to the glass wafer.
    Figure 2.4.
    Custom bonding setup built by Aurélien Mazzamurro, which served for anodically bond the SiC/Si stack to the glass wafer.
    1. The starting substrate is a 300-µm thick, 2-inch wide \langle 100\rangle intrinsic silicon wafer, with a high resistivity measured at more than 5000 Ω cm.
    2. A 1-µm 3C–SiC layer is grown by a two-step CVD, with propane and silane as chemical precursor, diluted in hydrogen. The depositing temperature is 1 150 °C in order to limit the thermal stress induced in the SC film. This step is performed by Marc Portail’s team at CRHEA.
    3. The film is chemomechanically polished by the subcontractor NovaSiC, creating a 0.6–0.8 nm Ra value, measured with an AFM scan over a 10 × 10 µm2 surface sample. The final surface resistivity is assessed using the non contact eddy current method, in the range of 1-10 Ω cm.
    4. The silicon side of the wafer was mechanically thinned on a Logitech PM5 lapping machine on a cast iron plate, using a slurry of 15 µm alumina particles. Reaching a 50 µm thickness, polishing is achieved on a felt plate with a Logitech SF1 alkaline colloidal silica slurry.
    5. Anodic bonding is performed on a in-house equipment designed and conceived and built by Aurélien Mazzamurro (figure 2.4). The polished silicon side is brought into contact with a MicroChemicals 4-inch 300-µm thick borosilicate wafer. The latter is grounded while a –1 kV potential is applied to the SiC/Si wafer, at a temperature of 350 °C. The electrical field moves Na+ ions, present in the borosilicate, away from the interface, while O2– ions are brought toward the Si/borosilicate interface, forming Si—O bonds and sealing the two surfaces together. The ion drift creates an electric current, which is monitored (figure ¿fig:ab_current?). When the residual current passes below 10 % of the initial current, the bonding process is considered completed, the whole process during about 15 minutes. The bonded stack (shown in figure figure ¿fig:bonded_stack?) is left slowly cooling on the bonder’s chucks.
    6. A first optical lithographic is performed. A LOR 10A / AZ 1512 photoresist bilayer is spin-coated on the silicon surface, with a 4-minute 180 °C and a 1-minute 110 °C prebake steps for each photoresist layer. On a Suss MA6/BA6 in hard contact mode, the photoresist is exposed with the contact pads design (purple layer shown in figure 2.2, on a positive mask). The design is then revealed using a AZ 726 MIF developer for 45 seconds. The photoresist opening are cleaned with a 30-second low-power O2 plasma.
    7. 250-nm thick gold pads are evaporated in a Plassys MEB550SL at a 5 nm/s rate, preceded by a 5 nm titanium adhesion layer. After lift-off in a heated SVC–14 solution, the contact pads are successfully patterned.
    8. A second optical lithographic process is performed. A 6-µm thick AZ 15nXT negative photoresist is spin-coated, followed by a 1-minute, 110 °C prebake step. The second lithographic mask (pink and brown layers shown in figure 2.2, on a negative mask) is used in the same fashion as in step 6. to produce the pattern. The photoresist is developed for 60 seconds with the AZ 326 MIF developer, and cleaned with the same O2 plasma.
    9. The SiC and Si layers are anisotropically etched on an Oxford Instruments PlasmaPro 100, using a C4F8 Bosch process consisting of cycles of SF6 and C4F8 passivation steps. Because there is no signal to indicate the etching progress, 150-cycle steps are performed, and the total cycle count falls between 500 and 600 cycles. As a result, the three wires are patterned in the SiC layer, sitting on top of 50-µm tall silicon walls.
    10. After photoresist stripping in acetone and isopropylic alcohol, a photoresist protective layer is applied and each individual chip diced.
    11. To release the wires, a final isotropic etching step is performed, using a 4.5 Torr XeF2 vapor on a Xactic Xetch machine. Four 10-second cycles are enough to obtain a ~10 µm lateral etching, achieving proper wire release.

    The resuting device is presented in figure ¿fig:calosic_si_glass?.